In digital signal receivers that receive synchronous digital signals, a symbol clock must be synchronized with the digital signal in order to recover information from the digital signal with minimal errors. Known means of synchronizing a symbol clock in a digital signal receiver include adjusting the symbol clock using zero crossing edges or stochastic gradient statistical techniques.
The zero crossing technique is widely used and quite simple, required only a few logic gates, or alternatively, programmed instructions and microprocessor cycles. However, when it is used with typical multilevel signals, timing phase jitter of the symbol clock is typically introduced by intersymbol interference caused by pre-transmission filtering or channel filtering characteristics. The intersymbol interference introduces the jitter into these zero crossing recovery circuits even when no noise has been introduced into the signal.
The stochastic gradient technique has been used in digital radio systems. A stochastic gradient technique described in U.S. patent application Ser. No. 08/401,467 filed Mar. 9, 1995, by Carsello, entitled "Selective Call Receiving Device with Improved Symbol Decoding and Automatic Frequency Control" works quite well, without introducing significant timing phase jitter. However, the technique is more sophisticated and requires significantly more logic circuits when implemented with hardware, or alternatively, requires significantly more programmed instructions and microprocessor cycles when implemented in software, than a zero crossing technique. Such additional complexity is appropriate in receivers that are designed using more advanced circuitry for other purposes, but may be inappropriate in simpler receivers.
Thus, what is needed is a technique that is simple to implement and which reduces timing phase jitter when compared to prior art techniques.